light_pwm.c 26 KB

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  1. /******************************************************************************
  2. * Copyright 2013-2014 Espressif Systems (Wuxi)
  3. *
  4. * FileName: user_light.c
  5. *
  6. * Description: light demo's function realization
  7. *
  8. * Modification history:
  9. * 2014/5/1, v1.0 create this file.
  10. *******************************************************************************/
  11. #include "ets_sys.h"
  12. #include "osapi.h"
  13. #include "os_type.h"
  14. #include "mem.h"
  15. #include "user_interface.h"
  16. #include "gpio.h"
  17. #include "driver/hw_timer.h"
  18. #include "light_pwm.h"
  19. #include "user_dbg.h"
  20. #if EP_PRJ_LIGHT_PWM
  21. #define MIN(x, y) ((x)<(y)?(x):(y))
  22. #define MAX(x, y) ((x)>(y)?(x):(y))
  23. // different cross zero wave. 1:always. 2:no-load/full-load/pwm affect zero. A:pulse. B:square wave
  24. // 1+A; 1+B; 2+A.
  25. // for one pulse every zero, 100Hz pulse, use Hi level to capture cross-zero.
  26. // 50Hz square wave means one edge every zero, use both P/N edge to capture.
  27. // default: anyedge. disable the macro INT_HILEVEL.
  28. #define CROSS_ZERO_INT_HILEVEL
  29. // #define CROSS_ZERO_INT_POSEDGE
  30. #define PWLDEV_INT_USE_MESSAGE
  31. #define SHINE_DISABLE_INT
  32. #if defined(PRJ_EMH02DE_V1)
  33. #define POWER_ON_AT_FRONT
  34. #endif
  35. // after power on or reset, wait for a while to count the pulse period. microsecond
  36. #define PWLDEV_CALCULATE_PERIOD_DELAY 1000
  37. #define LOG_CROSS_ZERO_TRIGGER // test code, record the time of every cross zero when calculate the period
  38. #define AP_SSID "MyIoTDemo"
  39. #define AP_PASSWORD "12345678"
  40. #define WEB_SERVER_PORT 80
  41. #define PWM_CHANNEL 1
  42. #define PWM_0_OUT_IO_MUX PERIPHS_IO_MUX_GPIO4_U
  43. #define PWM_0_OUT_IO_NUM 4
  44. #define PWM_0_OUT_IO_FUNC FUNC_GPIO4
  45. #define KEY_NUM 1
  46. #define KEY_0_IO_MUX PERIPHS_IO_MUX_MTDI_U
  47. #define KEY_0_IO_NUM 12
  48. #define KEY_0_IO_FUNC FUNC_GPIO12
  49. #define CROSS_ZERO_IO_MUX PERIPHS_IO_MUX_MTMS_U
  50. #define CROSS_ZERO_IO_NUM 14
  51. #define CROSS_ZERO_IO_FUNC FUNC_GPIO14
  52. #define FB_IO_MUX PERIPHS_IO_MUX_MTCK_U
  53. #define FB_IO_NUM 13
  54. #define FB_IO_FUNC FUNC_GPIO13
  55. #define RESET_IO_MUX PERIPHS_IO_MUX_MTDO_U
  56. #define RESET_IO_NUM 15
  57. #define RESET_IO_FUNC FUNC_GPIO15
  58. #define LED_IO_MUX PERIPHS_IO_MUX_GPIO5_U
  59. #define LED_IO_NUM 5
  60. #define LED_IO_FUNC FUNC_GPIO5
  61. typedef enum {
  62. WORK_INIT = 0,
  63. WORK_RESET_STAT,
  64. WORK_CALE_CROSS_ZERO,
  65. WORK_ON,
  66. WORK_OVERLOAD,
  67. WORK_UNLOAD,
  68. WORK_END
  69. } PWLDEV_WORK_TYPE;
  70. #define PWLDEV_STAT_BUFFSIZE 6
  71. typedef union {
  72. uint8 stat_data[PWLDEV_STAT_BUFFSIZE];
  73. struct {
  74. uint8 data0;
  75. uint8 data1;
  76. uint8 cmdtype;
  77. uint8 onoff;
  78. uint8 light;
  79. uint8 checksum;
  80. } stat_cfg;
  81. } pwldev_work_status;
  82. LOCAL pwldev_work_status pwldev_setting;
  83. LOCAL os_timer_t pwldev_pwm_timer;
  84. LOCAL os_timer_t pwldev_work_timer;
  85. os_event_t pwldev_procTaskQueue[PWLDEV_PROCTASK_QUEUELEN];
  86. #if defined(LOG_CROSS_ZERO_TRIGGER) /* added macro LOG_CROSS_ZERO_TRIGGER */
  87. #define CROSS_ZERO_LOG_MAX 200
  88. LOCAL uint32 cross_zero_tick[CROSS_ZERO_LOG_MAX]={0};
  89. #endif /* LOG_CROSS_ZERO_TRIGGER */
  90. LOCAL uint32 last_trigger_time = 0, current_trigger_time = 0;
  91. LOCAL uint32 cross_zero_period_min = 0;
  92. LOCAL uint32 cross_zero_period_max = 0;
  93. LOCAL uint16 cross_zero_tick_count = 0;
  94. LOCAL uint8 device_work_state = 0;
  95. LOCAL uint8 light_ctrl_start = 0;
  96. extern void user_webserver_init(uint32 port);
  97. LOCAL void pwldev_start_reset(void);
  98. #define pwldev_set_work_stat(stat) device_work_state = stat
  99. /******************************************************************************
  100. * Function
  101. *******************************************************************************/
  102. /******************************************************************************
  103. * FunctionName : user_ch_aircon_get_mode
  104. * Description : get mode
  105. * Parameters : NONE
  106. * Returns : uint8 :
  107. *******************************************************************************/
  108. uint8 ICACHE_FLASH_ATTR
  109. pwldev_get_cfg_onoff(void)
  110. {
  111. return pwldev_setting.stat_cfg.onoff;
  112. }
  113. uint8 ICACHE_FLASH_ATTR
  114. pwldev_get_cfg_light(void)
  115. {
  116. return pwldev_setting.stat_cfg.light;
  117. }
  118. uint8 ICACHE_FLASH_ATTR
  119. pwldev_get_cfg_fb(void)
  120. {
  121. return GPIO_INPUT_GET(GPIO_ID_PIN(FB_IO_NUM));
  122. }
  123. void ICACHE_FLASH_ATTR
  124. pwldev_set_cfg_onoff(uint8 on)
  125. {
  126. pwldev_setting.stat_cfg.onoff = on;
  127. }
  128. void ICACHE_FLASH_ATTR
  129. pwldev_set_cfg_light(uint8 light)
  130. {
  131. pwldev_setting.stat_cfg.light = light;
  132. }
  133. void ICACHE_FLASH_ATTR
  134. pwldev_set_cfg_reset(uint8 reset_level)
  135. {
  136. pwldev_setting.stat_cfg.data1 = reset_level;
  137. }
  138. void ICACHE_FLASH_ATTR
  139. pwldev_set_cfg_stoptick(uint8 value)
  140. {
  141. pwldev_setting.stat_cfg.data0 = value;
  142. }
  143. uint8 ICACHE_FLASH_ATTR
  144. pwldev_get_cfg_stoptick(uint8 value)
  145. {
  146. return pwldev_setting.stat_cfg.data0;
  147. }
  148. void ICACHE_FLASH_ATTR
  149. pwldev_change_light_config(void)
  150. {
  151. if(device_work_state != WORK_ON)
  152. return;
  153. os_timer_disarm(&pwldev_pwm_timer);
  154. os_timer_disarm(&pwldev_work_timer);
  155. #if defined(PRJ_EMH02DE_V1) /* added macro PRJ_EMH02DE_V1 */
  156. GPIO_OUTPUT_SET(RESET_IO_NUM, pwldev_setting.stat_cfg.data1);
  157. #endif /* PRJ_EMH02DE_V1 */
  158. os_printf("%s %d,%d\n",__func__, pwldev_setting.stat_cfg.onoff, pwldev_setting.stat_cfg.light);
  159. }
  160. #if defined(PRJ_EMH02DE_V1) /* added macro PRJ_EMH02DE_V1 */
  161. LOCAL void ICACHE_FLASH_ATTR
  162. pwldev_check_unload_cb(void)
  163. {
  164. EPIT_DBG("%s \n", __func__);
  165. os_timer_disarm(&pwldev_pwm_timer);
  166. os_timer_disarm(&pwldev_work_timer);
  167. pwldev_set_work_stat(WORK_UNLOAD);
  168. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_DISABLE);
  169. pwldev_start_reset();
  170. }
  171. LOCAL void ICACHE_FLASH_ATTR
  172. pwldev_overload_check_handle(void)
  173. {
  174. uint32 gpio_status;
  175. gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  176. if(gpio_status & BIT(CROSS_ZERO_IO_NUM))
  177. {
  178. #if defined(PRJ_EMH02DE_V1) /* added macro PRJ_EMH02DE_V1 */
  179. if(1 == GPIO_INPUT_GET(GPIO_ID_PIN(CROSS_ZERO_IO_NUM)))
  180. {
  181. #if defined(CROSS_ZERO_INT_HILEVEL) /* added macro CROSS_ZERO_INT_HILEVEL */
  182. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_LOLEVEL);
  183. #endif /* CROSS_ZERO_INT_HILEVEL */
  184. }
  185. else
  186. {
  187. #if defined(CROSS_ZERO_INT_HILEVEL) /* added macro CROSS_ZERO_INT_HILEVEL */
  188. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_HILEVEL);
  189. #endif /* CROSS_ZERO_INT_HILEVEL */
  190. }
  191. os_timer_disarm(&pwldev_pwm_timer);
  192. os_timer_setfn(&pwldev_pwm_timer, (os_timer_func_t *)pwldev_check_unload_cb, NULL);
  193. os_timer_arm(&pwldev_pwm_timer, 100, 0);
  194. #else
  195. #endif /* PRJ_EMH02DE_V1 */
  196. }
  197. // Clear interrupt status
  198. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, gpio_status);
  199. }
  200. LOCAL void ICACHE_FLASH_ATTR
  201. pwldev_goto_overload(void)
  202. {
  203. EPIT_DBG("%s \n", __func__);
  204. os_timer_disarm(&pwldev_pwm_timer);
  205. os_timer_disarm(&pwldev_work_timer);
  206. ETS_GPIO_INTR_DISABLE();
  207. ETS_GPIO_INTR_ATTACH(pwldev_overload_check_handle, NULL);
  208. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_ANYEDGE);
  209. ETS_GPIO_INTR_ENABLE();
  210. os_timer_disarm(&pwldev_pwm_timer);
  211. os_timer_setfn(&pwldev_pwm_timer, (os_timer_func_t *)pwldev_check_unload_cb, NULL);
  212. os_timer_arm(&pwldev_pwm_timer, 100, 0);
  213. }
  214. LOCAL void pwldev_pwm_handler_enable_int(void)
  215. {
  216. #if defined(SHINE_DISABLE_INT) /* added macro SHINE_DISABLE_INT */
  217. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_HILEVEL);
  218. #endif /* SHINE_DISABLE_INT */
  219. }
  220. static void pwldev_pwm_handler_hi(void)
  221. {
  222. // if(set_cfg_ins++<100)
  223. // {
  224. // EPIT_DBG("TMe%d\n",set_cfg_ins);
  225. // }
  226. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 0);
  227. // hw_timer_set_func(pwldev_pwm_handler);
  228. // TODO: the period of pulse
  229. // hw_timer_arm(cross_zero_period_min/10*(10-pwldev_setting.stat_cfg.light));
  230. light_ctrl_start = 0;
  231. #if defined(SHINE_DISABLE_INT) /* added macro SHINE_DISABLE_INT */
  232. // gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_HILEVEL);
  233. hw_timer_set_func(pwldev_pwm_handler_enable_int);
  234. hw_timer_arm(100);
  235. #endif /* SHINE_DISABLE_INT */
  236. // #if defined(SHINE_CROSS_ZERO_INT_HI) /* added macro SHINE_CROSS_ZERO_INT_HI */
  237. // gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_HILEVEL);
  238. // #endif /* SHINE_CROSS_ZERO_INT_HI */
  239. }
  240. static void pwldev_pwm_handler(void)
  241. {
  242. // if(set_cfg_ins++<100)
  243. // {
  244. // EPIT_DBG("TMe%d\n",set_cfg_ins);
  245. // }
  246. // GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 0);
  247. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 1);
  248. hw_timer_set_func(pwldev_pwm_handler_hi);
  249. // // TODO: the period of pulse
  250. sint32 hi_period=cross_zero_period_min/10*(pwldev_setting.stat_cfg.light);
  251. // hw_timer_arm(hi_period>1000?hi_period-1000:(hi_period>>1));
  252. uint32 stop_period = pwldev_setting.stat_cfg.data0 * 20;
  253. uint32 low_period = cross_zero_period_min/10*(10-pwldev_setting.stat_cfg.light);
  254. hi_period = cross_zero_period_min - low_period - stop_period;
  255. if(hi_period<200)
  256. {
  257. EPIT_DBG("too small hi\n");
  258. hi_period=260;
  259. }
  260. hw_timer_arm(hi_period);
  261. // gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_POSEDGE);
  262. if(0 == GPIO_INPUT_GET(GPIO_ID_PIN(FB_IO_NUM)))
  263. {
  264. // pwm>1, fb<1, short circuit, overload. set pwm>0
  265. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 0);
  266. hw_timer_set_func(NULL);
  267. // check vin(cross_zero)
  268. }
  269. }
  270. #else
  271. void pwldev_pwm_handler(void)
  272. {
  273. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 1);
  274. }
  275. #endif
  276. LOCAL void ICACHE_FLASH_ATTR
  277. pwldev_shine_handle_msg(uint32 par)
  278. {
  279. uint32 stop_period;
  280. sint32 hi_period;
  281. uint32 time_delay;
  282. if(pwldev_setting.stat_cfg.onoff)
  283. {
  284. #if defined(PRJ_EMH02DE_V1) /* added macro PRJ_EMH02DE_V1 */
  285. // if((1 == GPIO_INPUT_GET(GPIO_ID_PIN(CROSS_ZERO_IO_NUM))))
  286. {
  287. stop_period = pwldev_setting.stat_cfg.data0 * 20;
  288. hi_period=cross_zero_period_min/10*(pwldev_setting.stat_cfg.light);
  289. #if defined(POWER_ON_AT_FRONT) /* added macro POWER_ON_AT_FRONT */
  290. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 1);
  291. if(pwldev_setting.stat_cfg.light < 10)
  292. {
  293. time_delay = hi_period - stop_period;
  294. }
  295. else
  296. {
  297. time_delay = cross_zero_period_min - stop_period;
  298. }
  299. hw_timer_set_func(pwldev_pwm_handler_hi);
  300. hw_timer_arm(time_delay);
  301. #else
  302. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 0);
  303. time_delay = cross_zero_period_min - hi_period;
  304. hw_timer_set_func(pwldev_pwm_handler);
  305. hw_timer_arm(time_delay);
  306. #endif /* POWER_ON_AT_FRONT */
  307. light_ctrl_start = 1;
  308. }
  309. /*
  310. */
  311. // reset timer to trigger unload state
  312. os_timer_disarm(&pwldev_pwm_timer);
  313. os_timer_setfn(&pwldev_pwm_timer, (os_timer_func_t *)pwldev_check_unload_cb, NULL);
  314. os_timer_arm(&pwldev_pwm_timer, 100, 0);
  315. if(0 == GPIO_INPUT_GET(GPIO_ID_PIN(FB_IO_NUM)) &&
  316. 1 == GPIO_INPUT_GET(GPIO_ID_PIN(PWM_0_OUT_IO_NUM)))
  317. {
  318. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_DISABLE);
  319. GPIO_OUTPUT_SET(RESET_IO_NUM, 0);
  320. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 0);
  321. pwldev_set_work_stat(WORK_OVERLOAD);
  322. os_timer_disarm(&pwldev_pwm_timer);
  323. os_timer_disarm(&pwldev_work_timer);
  324. os_timer_setfn(&pwldev_work_timer, (os_timer_func_t *)pwldev_goto_overload, NULL);
  325. os_timer_arm(&pwldev_work_timer, 2, 0);
  326. }
  327. #else
  328. // light_v01 2016-8-8
  329. if(pwldev_setting.stat_cfg.light < 10)
  330. {
  331. hi_period=cross_zero_period_min/10*(pwldev_setting.stat_cfg.light);
  332. time_delay = cross_zero_period_min - hi_period;
  333. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 0);
  334. hw_timer_set_func(pwldev_pwm_handler);
  335. hw_timer_arm(time_delay);
  336. }
  337. else
  338. {
  339. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 1);
  340. }
  341. #endif /* PRJ_EMH02DE_V1 */
  342. }
  343. else
  344. {
  345. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 0);
  346. #if defined(PRJ_EMH02DE_V1) /* added macro PRJ_EMH02DE_V1 */
  347. #if defined(SHINE_DISABLE_INT) /* added macro SHINE_DISABLE_INT */
  348. hw_timer_set_func(pwldev_pwm_handler_hi);
  349. hw_timer_arm(4000);
  350. #endif /* SHINE_DISABLE_INT */
  351. #endif /* PRJ_EMH02DE_V1 */
  352. }
  353. }
  354. #if defined(PWLDEV_INT_USE_MESSAGE)
  355. uint8 led_stat= 0;
  356. void pwldev_czero_shine(uint8 gpio_id)
  357. {
  358. uint32 gpio_status;
  359. gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  360. if(gpio_status & BIT(gpio_id))
  361. {
  362. #if defined(SHINE_DISABLE_INT) /* added macro SHINE_DISABLE_INT */
  363. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_DISABLE);
  364. #endif /* SHINE_DISABLE_INT */
  365. led_stat ^=1;
  366. GPIO_OUTPUT_SET(LED_IO_NUM, led_stat);
  367. system_os_post(PWLDEV_PROCTASK_PRIO, (os_signal_t)SIG_INT_TRIGGER, (os_param_t)0);
  368. }
  369. // Clear interrupt status
  370. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, gpio_status);
  371. }
  372. #else
  373. void pwldev_czero_shine(uint8 gpio_id)
  374. {
  375. uint32 gpio_status;
  376. gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  377. if(gpio_status & BIT(gpio_id))
  378. {
  379. if(pwldev_setting.stat_cfg.onoff)
  380. {
  381. if(pwldev_setting.stat_cfg.light < 10)
  382. {
  383. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 0);
  384. #if defined(PWLDEV_PWM_HW_TIMER) /* added macro PWLDEV_PWM_HW_TIMER */
  385. hw_timer_init(NMI_SOURCE, 0);
  386. hw_timer_set_func(pwldev_pwm_handler);
  387. // TODO: the period of pulse
  388. hw_timer_arm(1000*(10-pwldev_setting.stat_cfg.light));
  389. #else
  390. os_timer_disarm(&pwldev_pwm_timer);
  391. os_timer_setfn(&pwldev_pwm_timer, (os_timer_func_t *)pwldev_pwm_handler, NULL);
  392. os_timer_arm_us(&pwldev_pwm_timer, 1000*(10-pwldev_setting.stat_cfg.light), 0);
  393. #endif /* PWLDEV_PWM_HW_TIMER */
  394. }
  395. else
  396. {
  397. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 1);
  398. }
  399. }
  400. else
  401. {
  402. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 0);
  403. }
  404. }
  405. // Clear interrupt status
  406. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, gpio_status);
  407. }
  408. #endif
  409. LOCAL void pwldev_capture_int_enable_int(void)
  410. {
  411. #if defined(SHINE_DISABLE_INT) /* added macro SHINE_DISABLE_INT */
  412. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_HILEVEL);
  413. #endif /* SHINE_DISABLE_INT */
  414. }
  415. LOCAL void ICACHE_FLASH_ATTR
  416. pwldev_capture_int_handle_msg(void)
  417. {
  418. uint32 cross_zero_period_value = 0;
  419. current_trigger_time = system_get_time();
  420. if(cross_zero_tick_count++>5)
  421. {
  422. #if defined(LOG_CROSS_ZERO_TRIGGER) /* added macro LOG_CROSS_ZERO_TRIGGER */
  423. if(cross_zero_tick_count<CROSS_ZERO_LOG_MAX)
  424. cross_zero_tick[cross_zero_tick_count] = current_trigger_time;
  425. #endif /* LOG_CROSS_ZERO_TRIGGER */
  426. cross_zero_period_value = current_trigger_time - last_trigger_time;
  427. if(cross_zero_period_min)
  428. cross_zero_period_min = MIN(cross_zero_period_min, cross_zero_period_value);
  429. else
  430. cross_zero_period_min = cross_zero_period_value;
  431. cross_zero_period_max = MAX(cross_zero_period_max, cross_zero_period_value);
  432. }
  433. last_trigger_time = current_trigger_time;
  434. // gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_LOLEVEL);
  435. #if defined(SHINE_DISABLE_INT) /* added macro SHINE_DISABLE_INT */
  436. hw_timer_set_func(pwldev_capture_int_enable_int);
  437. hw_timer_arm(4000);
  438. #endif /* SHINE_DISABLE_INT */
  439. }
  440. LOCAL void ICACHE_FLASH_ATTR
  441. pwldev_procTask(os_event_t *events)
  442. {
  443. switch (events->sig) {
  444. case SIG_CAPTURE_INT:
  445. pwldev_capture_int_handle_msg();
  446. break;
  447. case SIG_INT_TRIGGER:
  448. pwldev_shine_handle_msg(events->par);
  449. break;
  450. case SIG_UART_GET_FRAME:
  451. break;
  452. case SIG_UART_UPDATE_STATUS:
  453. break;
  454. default:
  455. break;
  456. }
  457. }
  458. LOCAL void ICACHE_FLASH_ATTR
  459. pwldev_task_init(void)
  460. {
  461. system_os_task(pwldev_procTask, PWLDEV_PROCTASK_PRIO, pwldev_procTaskQueue, PWLDEV_PROCTASK_QUEUELEN);
  462. }
  463. LOCAL uint32 ICACHE_FLASH_ATTR
  464. pwldev_start_work(void)
  465. {
  466. EPIT_DBG("%s\n", __func__);
  467. #if 0
  468. os_timer_disarm(&pwldev_work_timer);
  469. ETS_GPIO_INTR_DISABLE();
  470. ETS_GPIO_INTR_ATTACH(pwldev_czero_shine, CROSS_ZERO_IO_NUM); // GPIO interrupt handler
  471. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_ANYEDGE);
  472. ETS_GPIO_INTR_ENABLE();
  473. device_work_state = WORK_ON;
  474. #endif
  475. os_timer_disarm(&pwldev_work_timer);
  476. ETS_GPIO_INTR_DISABLE();
  477. ETS_GPIO_INTR_ATTACH(pwldev_czero_shine, CROSS_ZERO_IO_NUM); // GPIO interrupt handler
  478. #if defined(SHINE_CROSS_ZERO_INT_HI) /* added macro SHINE_CROSS_ZERO_INT_HI */
  479. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_HILEVEL);
  480. // #else
  481. // gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_POSEDGE);
  482. // #endif /* SHINE_CROSS_ZERO_INT_HI */
  483. #else
  484. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_ANYEDGE);
  485. #endif
  486. ETS_GPIO_INTR_ENABLE();
  487. pwldev_set_work_stat(WORK_ON);
  488. EPIT_DBG("reggpio%d=%x\n", CROSS_ZERO_IO_NUM, GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(CROSS_ZERO_IO_NUM))));
  489. }
  490. /******************************************************************************
  491. * FunctionName : user_set_softap_config
  492. * Description : set SSID and password of ESP8266 softAP
  493. * Parameters : none
  494. * Returns : none
  495. *******************************************************************************/
  496. void ICACHE_FLASH_ATTR
  497. user_set_softap_config(void)
  498. {
  499. struct softap_config config;
  500. if(wifi_get_opmode() != SOFTAP_MODE)
  501. wifi_set_opmode(SOFTAP_MODE);
  502. os_memset(&config, 0, sizeof(config));
  503. wifi_softap_get_config(&config); // Get config first.
  504. os_sprintf(config.ssid, AP_SSID);
  505. os_sprintf(config.password, AP_PASSWORD);
  506. config.ssid_len = os_strlen(config.ssid);
  507. config.authmode = AUTH_WPA_WPA2_PSK;
  508. config.beacon_interval = 100;
  509. config.max_connection = 4; // how many stations can connect to ESP8266 softAP at most.
  510. wifi_softap_set_config(&config);// Set ESP8266 softap config .
  511. }
  512. LOCAL uint32 ICACHE_FLASH_ATTR
  513. user_get_rtc_ms(void)
  514. {
  515. uint32 cal2 = system_rtc_clock_cali_proc();
  516. // os_printf("cal 2 : %d.%d \r\n",((cal2*1000)>>12)/1000,
  517. // ((cal2*1000)>>12)%1000 );
  518. uint32 rtc_t2 = system_get_rtc_time();
  519. uint64 time_acc = ( ((uint64)(rtc_t2)) * ( (uint64)((cal2*1000)>>12)) ) ;
  520. return (uint32)(time_acc/1000000);
  521. }
  522. LOCAL void ICACHE_FLASH_ATTR
  523. pwldev_check_cross_zero_tick(void)
  524. {
  525. #if defined(LOG_CROSS_ZERO_TRIGGER) /* added macro LOG_CROSS_ZERO_TRIGGER */
  526. uint8 i;
  527. for(i=0; i<(cross_zero_tick_count<CROSS_ZERO_LOG_MAX?cross_zero_tick_count:CROSS_ZERO_LOG_MAX); i++)
  528. {
  529. EPIT_DBG("zt[%02d]=%d\n", i, cross_zero_tick[i]);
  530. }
  531. #endif /* LOG_CROSS_ZERO_TRIGGER */
  532. EPIT_DBG("cross_zero_period_min=%d,cross_zero_tick_count=%d\n", cross_zero_period_min,cross_zero_tick_count);
  533. EPIT_DBG("cross_zero_period_max=%d,cross_zero_tick_count=%d\n", cross_zero_period_max,cross_zero_tick_count);
  534. pwldev_start_work();
  535. }
  536. #if 0
  537. // calculate AC is 50/60 Hz ?
  538. void capture_cross_zero(uint8 gpio_id)
  539. {
  540. uint32 gpio_status;
  541. gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  542. if(gpio_status & BIT(gpio_id))
  543. {
  544. #if defined(LOG_CROSS_ZERO_TRIGGER) /* added macro LOG_CROSS_ZERO_TRIGGER */
  545. cross_zero_tick[cross_zero_tick_count++] = system_get_time();
  546. #endif /* LOG_CROSS_ZERO_TRIGGER */
  547. if(cross_zero_tick_count>=20)
  548. {
  549. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_DISABLE);
  550. os_timer_disarm(&pwldev_pwm_timer);
  551. os_timer_setfn(&pwldev_pwm_timer, (os_timer_func_t *)pwldev_check_cross_zero_tick, NULL);
  552. os_timer_arm(&pwldev_pwm_timer, 10, 0);
  553. }
  554. }
  555. // Clear interrupt status
  556. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, gpio_status);
  557. }
  558. LOCAL uint32 ICACHE_FLASH_ATTR
  559. pwldev_prepare_work(void)
  560. {
  561. EPIT_DBG("%s\n", __func__);
  562. os_timer_disarm(&pwldev_work_timer);
  563. if(device_work_state == WORK_ON)
  564. {
  565. return;
  566. }
  567. else if(device_work_state == WORK_CALE_CROSS_ZERO)
  568. {
  569. EPIT_DBG("%s stop cap zero\n", __func__);
  570. ETS_GPIO_INTR_DISABLE();
  571. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_DISABLE);
  572. ETS_GPIO_INTR_ENABLE();
  573. pwldev_check_cross_zero_tick();
  574. }
  575. pwldev_start_work();
  576. }
  577. #endif
  578. LOCAL void ICACHE_FLASH_ATTR
  579. user_start(void)
  580. {
  581. os_printf("%s\n", __func__);
  582. #if 0
  583. os_timer_disarm(&pwldev_work_timer);
  584. os_timer_setfn(&pwldev_work_timer, (os_timer_func_t *)pwldev_prepare_work, NULL);
  585. os_timer_arm(&pwldev_work_timer, 1000, 0);
  586. #endif
  587. }
  588. LOCAL uint32 ICACHE_FLASH_ATTR
  589. pwldev_stop_capture_cross_zero(void)
  590. {
  591. EPIT_DBG("%s\n", __func__);
  592. os_timer_disarm(&pwldev_work_timer);
  593. #if defined(PRJ_EMH02DE_V1) /* added macro PRJ_EMH02DE_V1 */
  594. os_timer_disarm(&pwldev_pwm_timer);
  595. #endif /* PRJ_EMH02DE_V1 */
  596. #if defined(SHINE_DISABLE_INT) /* added macro SHINE_DISABLE_INT */
  597. hw_timer_set_func(NULL);
  598. #endif /* SHINE_DISABLE_INT */
  599. ETS_GPIO_INTR_DISABLE();
  600. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_DISABLE);
  601. ETS_GPIO_INTR_ENABLE();
  602. if(cross_zero_period_min)
  603. {
  604. pwldev_check_cross_zero_tick();
  605. }
  606. else
  607. {
  608. // if no load, cross zero(vin) always high, cross_zero_period_min=0 is invalid.
  609. // keep on reset state.
  610. pwldev_start_reset();
  611. }
  612. }
  613. #if defined(PWLDEV_INT_USE_MESSAGE)
  614. void capture_cross_zero_pulse(uint8 gpio_id)
  615. {
  616. uint32 gpio_status;
  617. gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  618. if(gpio_status & BIT(gpio_id))
  619. {
  620. #if defined(SHINE_DISABLE_INT) /* added macro SHINE_DISABLE_INT */
  621. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_DISABLE);
  622. #endif /* SHINE_DISABLE_INT */
  623. system_os_post(PWLDEV_PROCTASK_PRIO, (os_signal_t)SIG_CAPTURE_INT, (os_param_t)0);
  624. }
  625. // Clear interrupt status
  626. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, gpio_status);
  627. }
  628. #else
  629. void capture_cross_zero_pulse(uint8 gpio_id)
  630. {
  631. uint32 gpio_status;
  632. uint32 cross_zero_period_value = 0;
  633. gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  634. if(gpio_status & BIT(gpio_id))
  635. {
  636. #if defined(CROSS_ZERO_INT_HILEVEL) /* added macro CROSS_ZERO_INT_HILEVEL */
  637. if(1 == GPIO_INPUT_GET(GPIO_ID_PIN(CROSS_ZERO_IO_NUM)))
  638. {
  639. current_trigger_time = system_get_time();
  640. if(cross_zero_tick_count++>5)
  641. {
  642. #if defined(LOG_CROSS_ZERO_TRIGGER) /* added macro LOG_CROSS_ZERO_TRIGGER */
  643. if(cross_zero_tick_count<CROSS_ZERO_LOG_MAX)
  644. cross_zero_tick[cross_zero_tick_count] = current_trigger_time;
  645. #endif /* LOG_CROSS_ZERO_TRIGGER */
  646. cross_zero_period_value = current_trigger_time - last_trigger_time;
  647. if(cross_zero_period_min)
  648. cross_zero_period_min = MIN(cross_zero_period_min, cross_zero_period_value);
  649. else
  650. cross_zero_period_min = cross_zero_period_value;
  651. cross_zero_period_max = MAX(cross_zero_period_max, cross_zero_period_value);
  652. }
  653. last_trigger_time = current_trigger_time;
  654. // gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_LOLEVEL);
  655. }
  656. else
  657. {
  658. // gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_HILEVEL);
  659. }
  660. #else /* */
  661. current_trigger_time = system_get_time();
  662. if(cross_zero_tick_count++>5)
  663. {
  664. #if defined(LOG_CROSS_ZERO_TRIGGER) /* added macro LOG_CROSS_ZERO_TRIGGER */
  665. if(cross_zero_tick_count<CROSS_ZERO_LOG_MAX)
  666. cross_zero_tick[cross_zero_tick_count] = current_trigger_time;
  667. #endif /* LOG_CROSS_ZERO_TRIGGER */
  668. cross_zero_period_value = current_trigger_time - last_trigger_time;
  669. if(cross_zero_period_min)
  670. cross_zero_period_min = MIN(cross_zero_period_min, cross_zero_period_value);
  671. else
  672. cross_zero_period_min = cross_zero_period_value;
  673. cross_zero_period_max = MAX(cross_zero_period_max, cross_zero_period_value);
  674. }
  675. last_trigger_time = current_trigger_time;
  676. #endif /* CROSS_ZERO_INT_HILEVEL */
  677. #if defined(PRJ_EMH02DE_V1) /* added macro PRJ_EMH02DE_V1 */
  678. os_timer_disarm(&pwldev_pwm_timer);
  679. os_timer_setfn(&pwldev_pwm_timer, (os_timer_func_t *)pwldev_check_unload_cb, NULL);
  680. os_timer_arm(&pwldev_pwm_timer, 100, 0);
  681. #endif /* PRJ_EMH02DE_V1 */
  682. }
  683. // Clear interrupt status
  684. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, gpio_status);
  685. #if defined(CROSS_ZERO_INT_HILEVEL) /* added macro CROSS_ZERO_INT_HILEVEL */
  686. if(1 == GPIO_INPUT_GET(GPIO_ID_PIN(CROSS_ZERO_IO_NUM)))
  687. {
  688. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_LOLEVEL);
  689. }
  690. else
  691. {
  692. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_HILEVEL);
  693. }
  694. #endif /* CROSS_ZERO_INT_HILEVEL */
  695. }
  696. #endif
  697. // after reset, get the period of cross zero pulse
  698. LOCAL void ICACHE_FLASH_ATTR
  699. pwldev_reset_check_cross_zero(void)
  700. {
  701. os_timer_disarm(&pwldev_work_timer);
  702. cross_zero_period_min = 0;
  703. cross_zero_period_max = 0;
  704. cross_zero_tick_count = 0;
  705. #if defined(PRJ_EMH02DE_V1) /* added macro PRJ_EMH02DE_V1 */
  706. GPIO_OUTPUT_SET(RESET_IO_NUM, 0);
  707. #endif /* PRJ_EMH02DE_V1 */
  708. ETS_GPIO_INTR_DISABLE();
  709. ETS_GPIO_INTR_ATTACH(capture_cross_zero_pulse, CROSS_ZERO_IO_NUM); // GPIO interrupt handler
  710. #if defined(CROSS_ZERO_INT_HILEVEL) /* added macro CROSS_ZERO_INT_HILEVEL */
  711. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_HILEVEL);
  712. #elif defined(CROSS_ZERO_INT_POSEDGE)
  713. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_POSEDGE);
  714. #else
  715. gpio_pin_intr_state_set(GPIO_ID_PIN(CROSS_ZERO_IO_NUM), GPIO_PIN_INTR_ANYEDGE);
  716. #endif /* CROSS_ZERO_INT_HILEVEL */
  717. ETS_GPIO_INTR_ENABLE();
  718. os_timer_setfn(&pwldev_work_timer, (os_timer_func_t *)pwldev_stop_capture_cross_zero, NULL);
  719. os_timer_arm(&pwldev_work_timer, PWLDEV_CALCULATE_PERIOD_DELAY, 0);
  720. #if defined(PRJ_EMH02DE_V1) /* added macro PRJ_EMH02DE_V1 */
  721. os_timer_disarm(&pwldev_pwm_timer);
  722. os_timer_setfn(&pwldev_pwm_timer, (os_timer_func_t *)pwldev_check_unload_cb, NULL);
  723. os_timer_arm(&pwldev_pwm_timer, 100, 0);
  724. #endif /* PRJ_EMH02DE_V1 */
  725. }
  726. // output 10ms high pulse to reset the mosfet
  727. LOCAL void ICACHE_FLASH_ATTR
  728. pwldev_start_reset(void)
  729. {
  730. EPIT_DBG("%s\n", __func__);
  731. #if defined(PRJ_EMH02DE_V1) /* added macro PRJ_EMH02DE_V1 */
  732. pwldev_set_work_stat(WORK_RESET_STAT);
  733. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 0);
  734. GPIO_OUTPUT_SET(RESET_IO_NUM, 1);
  735. #endif /* PRJ_EMH02DE_V1 */
  736. os_timer_disarm(&pwldev_work_timer);
  737. os_timer_setfn(&pwldev_work_timer, (os_timer_func_t *)pwldev_reset_check_cross_zero, NULL);
  738. os_timer_arm(&pwldev_work_timer, 10, 0);
  739. }
  740. LOCAL void ICACHE_FLASH_ATTR
  741. pwldev_io_init(void)
  742. {
  743. PIN_FUNC_SELECT(CROSS_ZERO_IO_MUX, CROSS_ZERO_IO_FUNC);
  744. GPIO_DIS_OUTPUT(CROSS_ZERO_IO_NUM);
  745. PIN_FUNC_SELECT(PWM_0_OUT_IO_MUX, PWM_0_OUT_IO_FUNC);
  746. GPIO_OUTPUT_SET(PWM_0_OUT_IO_NUM, 0);
  747. #if defined(PRJ_EMH02DE_V1) /* added macro PRJ_EMH02DE_V1 */
  748. PIN_FUNC_SELECT(FB_IO_MUX, FB_IO_FUNC);
  749. GPIO_DIS_OUTPUT(FB_IO_NUM);
  750. PIN_FUNC_SELECT(RESET_IO_MUX, RESET_IO_FUNC);
  751. GPIO_OUTPUT_SET(RESET_IO_NUM, 0);
  752. PIN_FUNC_SELECT(LED_IO_MUX, LED_IO_FUNC);
  753. GPIO_OUTPUT_SET(LED_IO_NUM, 0);
  754. #endif /* PRJ_EMH02DE_V1 */
  755. }
  756. /******************************************************************************
  757. * FunctionName : user_ch_aircon_init
  758. * Description : light demo init
  759. * Parameters : none
  760. * Returns : none
  761. *******************************************************************************/
  762. void ICACHE_FLASH_ATTR
  763. pwldev_init(void)
  764. {
  765. os_memset(&pwldev_setting, 0, sizeof(pwldev_setting));
  766. pwldev_io_init();
  767. hw_timer_init(FRC1_SOURCE, 0); //NMI_SOURCE
  768. pwldev_task_init();
  769. pwldev_start_reset();
  770. user_set_softap_config();
  771. user_webserver_init(WEB_SERVER_PORT);
  772. system_init_done_cb(user_start);
  773. }
  774. #endif